library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;

package pack is
  -- XST13 + Synplify: OK  
  TYPE array_typ1 is array (natural range <>) of std_logic;

  -- XST13 + Synplify: OK  
  TYPE array_typ2 is array (natural range <>, natural range <>) of std_logic;

  -- XST13 default: Fehler  / Synplify: OK  / XST13 mit "-use_new_parser yes": OK
  TYPE array_typ3 is array (natural range <>, natural range <>, natural range <>) of std_logic;
  
  -- XST13 default: Fehler  / Synplify: OK  / XST13 mit "-use_new_parser yes": OK
  TYPE array_typ4 is array (natural range <>, natural range <>, natural range <>, natural range <>) of std_logic;
  
  -- XST13 default: Fehler  / Synplify: OK  / XST13 mit "-use_new_parser yes": OK
  TYPE array_typ5 is array (natural range <>, natural range <>, natural range <>, natural range <>, natural range <>) of std_logic;
end pack;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.pack.all;

entity PackageTypedef is
    generic ( ca : integer := 4;
              cb : integer := 3;
              cc : integer := 2;
              cd : integer := 1;
              ce : integer := 2 );
    
    Port ( clk  : in  STD_LOGIC;
           din  : in  std_logic_vector((ca+1)*(cb+1)*(cc+1)*(cd+1)*(ce+1) downto 0);
           tt1  : out array_typ1 (ca downto 0);
           tt2  : out array_typ2 (ca downto 0, cb downto 0);
           tt3  : out array_typ3 (ca downto 0, cb downto 0, cc downto 0);  
           tt4  : out array_typ4 (ca downto 0, cb downto 0, cc downto 0, cd downto 0);  
           tt5  : out array_typ5 (ca downto 0, cb downto 0, cc downto 0, cd downto 0, ce downto 0) );  
end PackageTypedef;

architecture Behavioral of PackageTypedef is
begin
   b1: for i in 0 to ca generate
     tt1(i) <= din(i);
   end generate b1;

   h1: for i in 0 to ca generate
     h2: for j in 0 to cb generate
       tt2(i,j) <= din(i+j*ca);
     end generate h2;
   end generate h1;

   i1: for i in 0 to ca generate
     i2: for j in 0 to cb generate
       i3: for k in 0 to cc generate
         tt3(i,j,k) <= din(i+j*ca+k*ca*cb);
       end generate i3;
     end generate i2;
   end generate i1;

   n1: for i in 0 to ca generate
     n2: for j in 0 to cb generate
       n3: for k in 0 to cc generate
         n4: for l in 0 to cd generate
           tt4(i,j,k,l) <= din(i+j*ca+k*ca*cb+l*ca*cb*cc);
         end generate n4;
       end generate n3;
     end generate n2;
   end generate n1;
   
   p1: for i in 0 to ca generate
     p2: for j in 0 to cb generate
       p3: for k in 0 to cc generate
         p4: for l in 0 to cd generate
           p5: for m in 0 to ce generate
             tt5(i,j,k,l,m) <= din(i+j*ca+k*ca*cb+l*ca*cb*cc+m*ca*cb*cc*cd);
           end generate p5;
         end generate p4;
       end generate p3;
     end generate p2;
   end generate p1;
end Behavioral;